1. Field of the Invention
The invention relates to wiring method, program, and apparatus in a layout design of an LSI and, more particularly, to wiring method, program, and apparatus which enable a high-speed wiring process at a high density.
2. Description of the Related Arts
In recent years, with respect to an LSI designing system, a high-density designing system is required by micro miniaturization of a transistor size and a high-speed designing system which finishes a design in a shorter period of time is required by shortening a developing cycle. In association with it, automatic wiring of a high density and a high speed is demanded also in an automatic wiring system in the LSI designing system. In the automatic wiring system, the line connection among devices arranged by net information is processed so as to satisfy a designing rule and various restricting conditions and, ordinarily, it is processed separately with respect to global wiring and detailed wiring. According to the global wiring, each net is divided into specific wiring areas and the wirings are allocated, and which wiring area is used while avoiding a local jam is determined. According to the detailed wiring, actual wiring of each net is made and the nets between two points or among multi-points are sequentially wired one by one at the shortest distance. A labyrinth method, a line segment searching method, a channel wiring method, or the like is used as a wiring algorithm.
In the detailed wiring of such a conventional automatic wiring system, a method of setting the whole surface of a chip to a wiring area is used with respect to the wiring of one net.
Refer to JP-A-5-181936, JP-A-6-124321, JP-A-5-160375, JP-A-5-243383, JP-A-9-147009, JP-A-10-189746, and JP-A-2003-303217.
However, in such a conventional automatic wiring system, since the whole surface of the chip is set to the wiring area with respect to the wiring of one net, a wiring process according to the wiring algorithm such as labyrinth method, line segment searching method, channel wiring method, or the like is executed to the wide area of the whole chip surface as a target. Therefore, a processing time of the automatic wiring becomes long. When considering also the case where the wiring process is unsuccessful and, for example, the design is retried from an upstream such as a logic design or the like, there is such a problem that a TAT (Turn Around Time) of the LSI design itself is extended because it takes time for the automatic wiring.